1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly to a multi-chip package for implementing two or more semiconductor chips of different sizes and functions with one package.
2. Description of the Prior Art
In the semiconductor industry, the packaging technique for IC chips is continuously progressing. In particular, with the recent development of the information and communication industry, efforts have been continuously made to develop small, light and multifunctional packages. As a result of such efforts, a so-called xe2x80x9cmulti-chip packagexe2x80x9d has been proposed.
Such a multi-chip package is to increase memory capacity by stacking memory chips of a same size and function or to maximize the performance and efficiency of products by assembling various kinds of semiconductor chips of different sizes and functions. For example, two or more DRAMs are stacked to realize a high capacity, and a SRAM, a flash memory, an RF chip, etc. are simultaneously packaged and applied to a small and light portable communication device or the like.
There are many types of multi-chip packages according to their end-use products, makers, etc. Two typical examples of multi-chip packages according to the prior art are shown in FIGS. 1 and 2.
The conventional multi-chip package 10 shown in FIG. 1 is a type of thin small outline package (TSOP), in which individual packages 11, 12 are stacked. Whereas, the conventional multi-chip package shown in FIG. 2 is a type of ball grid array (BGA), in which individual semiconductor chips 21, 22, 23 are vertically stacked or horizontally arranged and then collectively packaged.
In the multi-chip package 10 shown in FIG. 10, the individual packages 11, 12 each comprise one semiconductor chip 10 and employ a lead-on-chip (LOC) lead frame. One or more internal leads 14 of the lead frame are adhered to the top surface of the semiconductor chip 13 by an adhesive tape and each electrically connected to the semiconductor chip 13 by a gold wire 16. The upper and lower stacked packages 11 and 12 are electrically interconnected by means of one or more separate connection leads 17. Herein, the connection leads 17 are bonded to one or more external leads 18 of each lead frame and serve as external connection terminals.
The multi-chip package 20 forms a single package, in which semiconductor chips 21, 22 and 23 are vertically stacked or horizontally arranged on one side of a printed circuit substrate 24. An adhesive 25 provides physical adhesion between the semiconductor chip 21 and the semiconductor chip 21 or between the semiconductor chips 21 and 22 and the semiconductor chip 23 and gold wires 26 provide electrical connection therebetween. The other side of the circuit substrate 24 is provided with solder balls that serve as external connection terminals.
The conventional multi-chip packages as described above have various disadvantages to be described below.
The multi-chip package 10 shown in FIG. 1 has a disadvantage in that its total height is increased because it is a package-stacked type. Therefore, it is difficult to apply the multi-chip package 10 of this type to a portable communication device. Furthermore, the chips 13 employed in the multi-chip package 10 must have a same size. If the chips 13 are of different sizes, the connection parts between the individual packages 11, 12 and/or between the external leads 18 and the interconnection leads 17 may be fractured due to a package warping phenomenon caused by the difference of thermal expansion coefficients thereof.
The multi-chip package 20 has a limit in vertically stacking the semiconductor chips 21, 22, 23. In this regard, if the semiconductor chips 21, 22, 23 are horizontally arranged, a problem arises in that the area of the multi-chip package 20 is increased. In addition, if memory chips of a same type are employed to increase the memory capacity, there will be a problem in that it is difficult to stack the chips as a result of the memory chips being same in size.
Meanwhile, the multi-chip packages shown in FIGS. 1 and 2 have a common problem in that they are not suitable for the products of high-speed devices because gold wires 16, 26 are used as electrical connection means.
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a multi-chip package, in which not only memory chips of a same type are stacked to be capable of increasing the memory capacity, but also memory chips of different types are compositely arranged to be capable of implementing a system-on-package having various functions.
It is also an object of the present invention to minimize the thickness and area of a multi-chip package, thereby enabling high integration of a system and to reduce the length of electrical connection passages to be capable of coping with a high-speed device.
It is another object of the present invention to reduce the weight of a multi-chip package in order to increase the competitiveness of a portable communication device or the like which employs the multi-chip package.
It is still another object of the present invention to enhance the reliability of a multi-chip package by removing a primary factor of degradation such as fracture of connection parts caused by a package warping phenomenon.
In order to accomplish the above objects, according to the present invention, there is provided a multi-chip package comprising: a circuit substrate consisting of first, second and third areas which surround three sides of the multi-chip package; and at least two semiconductor chips which are positioned within an internal space of the package defined by the internal surfaces of the above three areas, wherein the semiconductor chips are physically bonded and electrically connected to each other.
In the multi-chip package according to the present invention, the circuit substrate comprises a plurality of substrate pads which are formed on the internal surfaces of the above three areas and electrically connected to the semiconductor chips. The semiconductor chips comprises a plurality of chip pads formed on the top surfaces of the semiconductor chips and a plurality of chip bumps individually formed on each of the chip pads, respectively corresponding chip bumps and substrate pads being physically bonded and electrically connected to each other.
In addition, the semiconductor chips comprises a first semiconductor chip provided on the first area, at least one second semiconductor chip provided on the second area, and a third semiconductor chip provided on the third area. Herein, a rear surface of the first semiconductor chip is faced to a rear surface of the third semiconductor chip and the first semiconductor chip and the third semiconductor chip may have an identical size.
Meanwhile, the circuit substrate may comprise a plurality of ball lands, which are formed on the external surface of the first area and electrically connected to the substrate pads, and in this case a plurality of solder balls may be respectively formed on the ball lands.
In addition, the circuit substrate may further comprise a fourth area which extends from a side of the third area and the fourth area may comprise a plurality of contact pads which are formed on a side of the four area and electrically connected to the substrate pads.
The circuit substrate preferably comprises a plurality of notches formed in the external surfaces of first, second and third areas at the boundaries of these three areas and the multi-chip package may further comprise an encapsulant filled in the internal space of the package.
According to another aspect of the present invention, there is provided a method for manufacturing a multi-chip package, comprising the steps of: providing a circuit substrate consisting of first, second and third areas; bonding two or more semiconductor chips to the internal surfaces of the above three areas so that those chips are physically bonded and electrically connected to the circuit substrate; and folding the circuit substrate so that the above three areas surround three sides of the package and the semiconductor chips are positioned within an internal space of the package defined by the internal surfaces of the three areas.
According to another aspect of the present invention, there is also provided a method for manufacturing a multi-chip package, comprising the steps of: providing a circuit substrate matrix formed with a plurality of unit circuit substrates, each substrate consisting of first, second and third areas; bonding two or more semiconductor chips to the internal surfaces of the above three areas of the unit circuit substrate, so that those chips are physically bonded and electrically connected to the unit circuit substrate; and folding the unit circuit substrate so that the above three areas surround three sides of the package and the semiconductor chips are positioned within an internal space of the package defined by the internal surfaces of the three areas.